# Advanced Packaging

TSMC's CoWoS (Chip on Wafer on Substrate) technology is the critical bottleneck for AI chip production, enabling the integration of multiple chiplets and HBM memory.

**Measure:** CoWoS & Advanced Chiplet Integration Capacity

**US & Allies Score:** 8.0/10  
**China Score:** 4.0/10  
**Leader:** US & Allies

## Key Metrics

- **Packaging throughput:** Throughput = (Packaged units/week) constrained by CoWoS lines, bump/TSV steps, and test capacity
- **Substrate constraint:** Constraint = min(ABF substrate supply, interposer capacity, packaging tool availability)

## What matters in this layer

Advanced chiplets trade monolithic scaling for integration complexity. Dominance comes from proven process recipes, low defectivity across large interposers, and a supply chain that can expand without breaking yields.

### CoWoS capacity as a gate

Even with ample wafer starts, GPU shipments can bottleneck on CoWoS throughput. Expansions depend on equipment and qualified operators, not only capex.

### Yield compounding

Multi‑die packages multiply yield loss modes. Small defect improvements compound into large effective output gains, especially for large HBM‑heavy packages.

## Recent Developments

### TSMC CoWoS Capacity Constrains AI Chip Supply
*3 days ago | Manufacturing*

TSMC is aggressively expanding CoWoS capacity, but demand continues to outstrip supply. The company expects to double capacity by 2025.

### Intel Advances Foveros 3D Packaging
*1 week ago | Technology*

Intel's Foveros technology enables face-to-face chip stacking, offering an alternative to TSMC's CoWoS for advanced AI chip integration.